In the advanced chip packaging methods, the WLP technique is a technique in which packaging and tests are performed on a semiconductor wafer and then the wafer is molded and singulated into individual IC packages.
FIG. 1 is a cross sectional diagram of a conventional semiconductor chip package. As shown in FIG. 1, the semiconductor chip package 200 includes package body 300 surrounding the semiconductor chip 100. In addition, the semiconductor chip package 200 includes metal contact pad 210 and passivation layer 220 formed on the top surface of the semiconductor chip 100, and the solder ball 230 formed on the top electrode of the semiconductor chip 100. A packaging method of forming the semiconductor chip package 200 is shown in FIG. 2. In step A1, a semiconductor wafer including a plurality semiconductor chips 100 are mounted onto a tape 400 with metal contact pad 210, passivation layer 220 and solder ball 230 formed on a front side of the chip 100. In step A2, the individual semiconductor chips 100 are separated by cutting through track 110 between two adjacent semiconductor chips 100, but the chips 100 still remain attached to tape 400. In step A3, plastic resin or other molding compound is filled into the dicing track 110 to form the plastic body 300. In step A4, individual semiconductor chip package 200 is separated from each other by sawing through a portion of the package body 300, thus the tape 400 is removed. However, the bottom of the semiconductor chip 100 of the chip package 200 is not encapsulated with plastic body 300, thus the semiconductor chip 100 is not completely protected.
FIG. 3 is a cross sectional diagram of another conventional semiconductor chip package 200. As shown in FIG. 3, the bottom and side of the semiconductor chip 100 are encapsulated with the plastic body 300. A packaging method for forming the chip package 200 of FIG. 3 is shown in FIG. 4. In Step B1 and B2, semiconductor chips 100 firstly attached on a tape 400 with the front side of each chip 100 facing downward, with a certain space between two adjacent chips 100. In step B3, a plastic material is deposited to fill into the space between adjacent chips 100 and to cover the back side of the semiconductor chip 100, which forms the plastic body 300. In step B4 and B5, the tape 400 is removed, then the whole structure, which include semiconductor chips 100 encapsulated by the plastic package body 300, is flipped. In step B6 and B7, fan-out RDL (Redistribution Layer) technique is applied to redistribute the electrode pads with metal contact pad 210 and passivation 220 formed on the front side of semiconductor chip 100. In step B8 and B9, solder balls 230 are placed on the front side of semiconductor chip 100 to form top electrode of chip package 200. After the chip package 200 is tested, individual chip packages 200 of the type shown in FIG. 3 are singulated. This semiconductor chip package 200 has plastic package protection on its side and bottom. However, the production process is very complicated.